1. Field of the Invention
The present invention relates to disk drives for computer systems. More particularly, the present invention relates to a disk drive implementing data path protection by encoding large host blocks into sub blocks.
2. Description of the Prior Art
Disk drives typically employ a number of interacting components that coordinate the transfer of data from a host during write operations, and the transfer of data read from the disk to the host during read operations. FIG. 1 shows an example of a prior art disk drive comprising one or more disks 2 and corresponding heads 3 enclosed in a head disk assembly (HDA) 4. The disk comprises a number of concentric, radially spaced data tracks, wherein each data track comprises a number of data sectors. A voice coil motor (VCM) 6 actuates the heads 3 over the disks 2 to access a target data sector within a target data track during write and read operations. A printed circuit board (PCB) is mounted to the HDA 4, wherein one or more integrated circuits for controlling operation of the disk drive are mounted on the PCB, including a microprocessor (uP) 8 for executing code segments of a control program. The microprocessor 8 typically accesses a fast uP cache 10 (e.g., an SRAM) through a uP cache controller 11 which caches op codes being executed as well as program data.
The code segments of the control program are typically stored on the disk 2 and loaded into an external buffer memory 12 (e.g., an SDRAM) when the disk drive is powered on. As the microprocessor 8 executes the control program, the uP cache controller 11 transfers a burst of corresponding op codes from the external buffer memory 12 into the uP cache 10 for fast access by the microprocessor 8. Since the buffer memory 12 is typically shared with other control components, a buffer controller 14 implements an arbitration algorithm to arbitrate access to the buffer memory 12. Example control components that may share access to the buffer memory 12 include a host interface 16, a disk interface 18, a data cache controller 20, and an ECC controller 22, one or more of which may be integrated with the microprocessor 8 in a system on a chip (SOC), or implemented as separate integrated circuits.
The host interface 16 facilitates data transfer between the disk drive and a host 24 during read and write operations. That is, during write operations the host interface 16 stages the data received from the host 24 in the buffer memory 12 before it is written to the disk 2, and during read operations data read from the disk 2 is staged in the buffer memory 12 before the host interface 16 transfers the read data to the host 24. The disk interface 18 performs the actual interface functions with the HDA 4 in order to write data stored in the buffer memory 12 to the disk 2, and store data into the buffer memory 12 that is read from the disk 2. The data cache controller 20 accesses a data cache area of the buffer memory 12 in order to implement a suitable caching algorithm, and the ECC controller 22 implements a suitable error correction algorithm on data read from the disk 2 and stored in the buffer memory 12.
The microprocessor 8 is typically preempted by a number of interrupts 26 for performing time critical operations in order to maintain optimal performance. For example, a servo controller 28 may generate an interrupt at each servo wedge, signaling the microprocessor 8 that it is time to compute an updated VCM 6 control command for servoing the head 3, or a spindle motor command for controlling the rotational speed of the disk 2. Preempting the microprocessor 8 in order to service the servo interrupts helps maintain optimal performance of the closed-loop servo systems.
The ever increasing complexity of the control program executed by the microprocessor 8 to coordinate the numerous components of the disk drive increases the probability of a programming error resulting in bad data being transferred to the host 24 during read operations. Defects in the integrated storage elements of the buffer memory 12 may also induce errors in the read data transferred to the host 24. To help protect against transferring bad data to the host 24, prior art disk drives have implemented “data path protection” techniques wherein the host block address received during a write operation is used by the host interface 16 to encode error detection code (EDC) data that is appended to the host block written to the disk 2. During a read operation of the host block, check data is generated using the host block address received from the host 24 to verify the integrity of the read data before it is transferred to the host 24. If the check data does not match the EDC data appended to the read host block, the disk drive may return an error to the host 24, or attempt a retry operation.
In prior art disk drives that employ data path protection techniques, each host block is typically mapped to a corresponding data sector. For example, a 512 byte host block may be mapped to a 516 byte data sector, wherein the additional 4 bytes of each data sector store the data path protection EDC data. However, disk drives are now being designed to receive and store host blocks that are significantly larger than the data sectors, for example 4096 byte host blocks. This creates a problem when implementing data path protection that generates EDC data using the host block address, if a large host block must be stored in a number of smaller data sectors.
There is, therefore, a need for a disk drive capable of implementing data path protection when a large host block is stored in a number of smaller data sectors.